1. Field of the Invention
This invention relates generally to semiconductor memory devices and more particularly to a precharge system for rapidly charging a bit line after switching from a write mode to a read mode.
2. Description of the Related Art
The access speed of a semiconductor memory device depends on the bit sensing operation when reading data from memory cells. When a semiconductor memory device is in a read mode, a pair of bit lines are typically precharged to a predetermined state at the beginning of a read cycle, so as to increase the speed of the bit sensing operation. However, in write mode, the individual bit lines of a bit line pair are driven to two different voltage levels, such that the bit lines must be precharged at the beginning of the next read mode. This decreases the data access speed. The data access speed further depends on the speed at which voltage differences are produced on data lines, i.e., the length of time required to change the voltage of the data lines from the precharged state to a readable logic level.
The bit line structure of a conventional semiconductor memory device is illustrated in FIG. 1. A memory cell 10 is connected between bit lines BL and /BL. A first precharge circuit 20 controllably connects the bit lines BL and /BL to a power supply voltage in response to a write control signal .phi.WE. The first precharge circuit 20 includes two PMOS transistors M1 and M2, each having a controlled current path connected between the bit lines BL and /BL, respectively, and the power source voltage. The gates of M1 and M2 are connected to the write control signal .phi.WE so as to precharge the bit lines BL and /BL in the read mode when the write control signal .phi.WE is turned off (deactivated). Thus, the first precharge circuit is switched to selectively precharge the bit lines.
A second precharge circuit 30 is connected between the bit lines BL and /BL and the power source voltage so as to precharge the bit lines. The second precharge circuit 30 includes two PMOS transistors M3 and M4, each having a controlled current source connected between the bit lines BL and /BL, respectively, and the power source voltage. The gates of transistors M3 and M4 are connected to a power supply ground voltage. Thus, the second precharge circuit 30 always precharges the bit lines with the power source voltage.
A column gate circuit 40 is connected between bit lines BL and /BL and a pair of data lines SDL and /SDL to controllably connect the bit lines with the data lines in response to a column select signal "Y". The column gate circuit 40 includes a first transfer gate TG1 connected between bit line BL and data line SDL, and a second transfer gate TG2 connected between bit line /BL and data line /SDL. The column gate circuit 40 is switched by the column select signal "Y" to connect the bit lines with the data lines so as to form a signal path between memory cell 10 and an external input/output pad.
A write and precharge circuit 50 transfers external input data from lines DIN and /DIN to the data lines SDL and /SDL in response to the write control signal .phi.WE. Circuit 50 includes two NAND gates NG1 and NG2 for driving the input data from lines DIN and /DIN onto the data lines SDL and /SDL, respectively, in response to the write control signal .phi.WE. The NAND gates NG1 and NG2 apply the external input data to the data lines when the write control signal .phi.WE is activated, i.e., driven to a high logic level. Circuit 50 also includes two PMOS transistors M5 and M6 connected between data lines SDL and /SDL, respectively, and the power source voltage. The gates of transistors M5 and M6 are connected to the write control signal .phi.WE. Another PMOS transistor M7 has a controlled current path connected between the data line SDL and /SDL and a gate connected to the write control signal .phi.WE. The PMOS transistors M5 and M6 precharge the data lines SDL and /SDL, respectively, with the power source voltage in the read mode when the write control signal .phi.WE is activated (i.e., driven to a low logic level). Transistor M7 equalizes the voltages of the data lines in the read mode.
A sense amplifier 60 amplifies the data from data lines SDL and /SDL and outputs the data to the input/output pad.
In operation, the write control signal .phi.WE of the conventional bit line circuit of FIG. 1 is activated, i.e., driven to a high logic level, during the write mode so that NAND gates NG1 and NG2 transfer input data from lines DIN and /DIN to the data lines SDL and /SDL, respectively. When the column select signal "Y" is enabled, i.e., driven to a high logic level, the column gate circuit 40 operates to connect data lines SDL and /SDL with bit lines BL and /BL, thereby transferring input data from lines DIN and /DIN into the memory cell 10.
When a read cycle is performed after a write cycle, the write control signal .phi.WE is disabled (driven to a low logic level) so that the first and second precharge circuits 20 and 30 and the write and precharge circuit 50 operate to precharge and equalize the highly imbalanced bit lines BL and /BL. More specifically, in the read mode, when the write control signal is driven to a low logic level, PMOS transistors M1 and M2 in precharge circuit 20 are turned on, thereby precharging BL and /BL to the power source voltage level. PMOS transistors M3 and M4 of circuit 30, which are always turned on, also operate to precharge the bit lines. Additionally, PMOS transistors M5 and M6 of the write and precharge circuit 50 are also turned on by the write control signal .phi.WE so as to precharge the data lines SDL and /SDL to the power source voltage level. Transistor M7 operates to equalize the voltages on the data lines in response to the write control signal.
Hence, the precharge circuits generally do not operate in the write mode, but instead are turned on to precharge and equalize the bit and data lines in the read mode. If the size of the transistors in the precharge circuits are increased, the bit lines will be precharged and equalized faster. However, large transistors would prevent a voltage difference from being produced on the bit lines during the read mode, thereby disabling the bit sensing operation. Therefore, in order to assure normal sensing operation of the bit lines, the sizes of transistors M1 to M7 must be kept small. Consequently, in such a conventional semiconductor memory device, the size of the precharge transistors is kept small resulting in a precharge time delay during a data access cycle and imperfect equalization.
Accordingly, a need remains for a method and apparatus for precharging lines in a semiconductor memory device which overcomes the above-mentioned problems.